The present invention relates to a mixer circuit arrangement and to an image-reject mixer circuit arrangement.
Mixer circuits for high frequency applications constructed using metal oxide semiconductor (MOS) transistors are subject to a limited voltage supply (usually less than 2 volts) and high levels of flicker noise, having frequencies extending up to several tens of MHz. Accordingly, the gain and output signal level required in such mixer circuits are greater than those required in the equivalent bipolar circuits.
It is known to construct a mixer circuit using MOS transistors using an arrangement translated directly from the conventional bipolar Gilbert cell mixer. Such MOS mixer circuits and modifications thereof are known from, for example, F. Behbahani, J. C. Lette, Y. Kishigami et al “A 2.4-GHz Low-IF Receiver for Wideband WLAN 0.6-um CMOS—Architecture and Front-End. “IEEE J. of Solid-State Circuits, vol. 35, pp. 1908–1916, December 2000; A. Rofouguran, G. Chang, J. J. Rael et al “A Single-Chip 900-MHz Spead-Spectrum Wireless Transceiver in I-um CMOS—Part II: Receiver Design.” IEEE J. of Solid-State Circuits, vol. 33, pp 535–547, April 1998; and A. N. Karanicolas “A 2.7-V 900-MHz CMOS LNA and Mixer.” IEEE J. of Solid-State Circuits, vol. 31, pp. 1939–944, December 1996. One such mixer circuit is shown schematically in FIG. 1.
Referring to FIG. 1, the mixer circuit 10 comprises generally first and second N-type MOS transistors TN1 and TN2, which constitute a transconductor and which have their control or gate electrodes connected to respective terminals 13, 14 of a different input RFN, RFP. A Gilbert cell mixer core is comprised of four further NMOS transistors 15 to 18, and a differential output is provided at terminals IFP, IFN between the mixer core and load resistors RL, which are also connected to a positive voltage supply VDD. The conversion gain of the mixer circuit 10 is moderately low, since the gain is proportional to the voltage headroom available. The mixer circuit, in effect, includes a transconductor, a mixer core and a load connected in series between the voltage supply terminals.
The arrangement described in the Karanicolas paper mentioned above has not proved to be practical since it requires approximately double the amount of headroom of the equivalent conventional circuit. Another mixer circuit is described in U.S. Pat. No. 5,768,700, and is shown schematically in FIG. 2.
Referring to FIG. 2, the mixer circuit 20 is shown comprising the FIG. 1 mixer circuit (reference numerals are retained for like elements), and a folded-cascode output stage comprising P type MOS transistors TP1 and TP2, load resistors RL2 and load capacitors CL. In this mixer circuit 20. the currents Io flowing through the transistors TP1 and TP2 can be significantly lower than those flowing through the mixer core, and it is therefore possible to have RL2>>RL1. Since the ac component of the output current of the mixer core is then directed largely to the output stage, a larger output signal is produced in comparison with the FIG. 1 mixer circuit. However, the mixer circuit 20 has relatively high current consumption because the transistors TN1 and TN2 must be biased with high dc currents in order to provide a linear current response. Also, the mixer core transistors 15 to 18 must perform hard switching of this high dc bias current, which requires the use of a powerful local oscillator (LO) driver.
Additional objects and advantages of the invention will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate at least one presently preferred embodiment of the invention as well as some alternative embodiments. These drawings, together with the description, serve to explain the principles of the invention but by no means are intended to be exhaustive of all of the possible manifestations of the invention.